1. Field of the Invention
The present invention relates to a semiconductor device and more particularly to a lateral static induction transistor used as a picture element of a solid state imaging device.
2. Description of the Prior Art
The basic construction of a conventional lateral static induction transistor (hereinafter simply referred to as an LSIT by using their first letters) is such that deposited by the addition of an impurity on a P-type (or N-type) semiconductor substrate, for example, is an N.sup.- (or P.sup.- if the substrate is N type) epitaxial layer formed opposite in conduction type to the semiconductor substrate, that N.sup.+ source and N.sup.+ drain zones are formed in the portions of the N.sup.- epitaxial layer near the surface thereof and that gate electrodes are formed through an insulating layer such as a silicon oxide layer on the N.sup.- epitaxial layer so as to respectively lie partially over the source zone and one of the drain zones. Then, the individual transistor elements are isolated electrically from one another by isolation zones formed in the epitaxial layer.
The fabrication of the LSIT constructed as described above is effected by first growing an N.sup.- epitaxial layer on a P-type semiconductor substrate, for example, and then performing such heat treatments as oxidation and diffusion so as to form source, drain and gate zones and an insulating layer.
Then, the channel of the LSIT is formed by the epitaxial layer of the opposite conduction type grown on the semiconductor substrate and it is known that small variations in the impurity concentration and thickness of the epitaxial layer have a great effect on the electric characteristics of the LSIT. For instance, if the N.sup.- epitaxial layer is high in impurity concentration or thickness, the LSIT has a normally -on characteristic (there is the flow of current between the source and the drain without the application of a voltage between the gate and the source. On the contrary, if the N.sup.- epitaxial layer is low in impurity concentration or thickness, the LSIT comes close to the normally-off characteristic (no current flows between the source and the drain unless a voltage is applied between the gate and the source).
Thus, in the case of the conventional LSIT such as mentioned above, due to the fact that the electric characteristics of the element are susceptible to the effect of variations in the physical properties of the epitaxial layer forming the channel, the problems which will be described hereunder are encountered in cases where a plurality of LSITs must be fabricated so as to be arranged one-dimensionally or two-dimentionally on the common semiconductor substrate, that is, where these LSITs are used for the picture elements of a solid state imaging device.
In other words, the semiconductor substrate generally involves impurity concentration variations, which are called as a striation, in small areas. If such impurity concentration variations are present in the semiconductor substrate, due to the heat treatments by the operations following the growing of the epitaxitial layer, the redistribution of the impurity concentration is caused at the boundary surface between the semiconductor substrate and the epitaxial layer and microscopically the thickness of the epitaxial layer varies from one small area to another. Where a plurality of LSITs are fabricated on the common semiconductor substrate, such thickness variations lead directly to variations in electric characteristics among the individual LSITs and therefore variations in electric characteristics are caused among the individual LSITs depending on their location on the substrate.
Thus, where the conventional LSITs are applied to the respective picture elements of a solid state imaging device, due to the variations in LSIT electric characteristics caused by the variations in impurity concentration among the different small areas of the semiconductor substrate, the solid state imaging device is caused to produce a large FPN (fixed pattern noise).